Abstract
In the development of new microprocessors, quantitative evaluation is possible only by using simulator. However, different users have various requirements for the simulator. The trade-off between simulation time and flexibility is the most important decision for any simulators. This paper presents a deliberate design to achieve those goals at the same time. For fast simulation speed, we provide a performance model to analysis a simulator, and innovate an executable control flow graph (ECFG). Furthermore, we also propose an effective way to improve the performance of a simulator. For high precision, our simulator is able to simulate the clock edge event and to expose detail register and memory information. For high flexibility, we present a layered approach that can be extended to any kind of emulator, even thought a GNU debugger (GDB) or a test suite. Besides the performance and extension issues, this paper also collects, describes, applies, and compares various simulation techniques to aid the simulator architects in selecting the most appropriate one. We apply these techniques to the Starfish DSP simulator.