Abstract
Frequency synthesizer is in charge of generating a high quality signal source for passband transceiver up- and down-conversions. For a high resolution synthesizer design, the Σ-Δ fractional-N structure is widely adopted. Combining a Σ-Δ modulator with the multi-modulus divider, a frequency divider is capable of emulating fractional multiple of reference frequency in the PLL output. However, the fractional error, which inevitably comes from the timing quantization, dominates the PLL output noise and limits the loop bandwidth. In this thesis, efforts are dedicated to the reduction of fractional error for PLL bandwidth extension. A new fractional division technique is proposed and implemented in TSMC 0.18μm CMOS process. By applying the direct synthesis circuit in PLL, a nearly true fractional divider can be achieved. The fractional error is compensated via phase interpolation and the error reduction can be conceptually proven by behavioral simulation. The idea is validated in silicon measurement. In this work, a fractional-N frequency synthesizer is realized. Measurement results show that the synthesizer can generate frequency signals ranging from 4.63GHz to 5.56GHz with 18.6KHz output frequency resolution and 16μsec settling time. The in-band phase noise can achieve -80dBc/Hz. Chip area of this synthesizer is 2.1mm2, including I/O pad. This circuit consumes a power of 52.8mW under normal operation. During the design and measurement, some practical issues about this architecture are also discovered. The suitable applications are therefore restricted. Toward those issues, some discussions are addressed for the future improvement.