Abstract
Embedded memory blocks in FPGAs allow designers to implement a variety of memory structures. With the increasing use of embedded memory blocks, the power consumed by them has formed a significant part of the total dynamic power consumption. In this thesis, we present a power-aware memory mapping algorithm, which maps user-defined logical memories to physical embedded memory blocks under the memory resource constraint. Our algorithm converts the memory mapping problem to a generalized network flow (GNF) problem, which can distribute embedded memory blocks to all logical memories at the same time. Our algorithm is compared with an existing method, and the promising experimental results show that our algorithm can always efficiently generate optimal solutions while the existing method cannot.