Abstract
We propose a hardware accelerator for Context-based Adaptive Binary Arithmetic decoding (CABAC) in H.264/AVC. We also propose an efficient memory system for easy integration with other components such as motion compensation and IDCT. For getting neighboring data, we propose a pipelined architecture to reduce clock cycles. We develop an efficient finite state machine so that our design can generate one bit every 2 to 3 clock cycles. Our design is verified in FPGA prototyping by using an ARM integrator. Experimental result shows that our design is capable of decoding main profile 720P (1280 x 720) video stream at 30 fps.