Abstract
In this thesis, the hardware-efficient Fast Fourier Transform (FFT) processor with flexible point-lengths is proposed to penetrate into applications of variable MIMO-OFDM (Orthogonal Frequency Division Multiplexing) system, one of the principle technologies in recent wireless communications, and is demonstrated especially suitable for the WMAN/WLAN/UWB. The databases are specified for WMAN/WLAN/UWB systems, defined by IEEE 802.16e/802.11n/802.15.3a standards which were based on IEEE work group, respectively. This study employed the multi-path delay feedback (MDF) of pipeline architecture into memory-based FFT processor to raise its throughput-rate (T.R.). In order to achieve SQNR requirements, the block scaling and multi-data scaling methods were used in the proposed FFT kernel. In behalf of reducing hardware cost, the interleave caches were utilized for decreasing memory access times and sharing calculating units. Finally, the single-port SRAM was introduced into the presented architecture with optimized memory-access scheme for multi-path processing. The test chip has been successfully designed and fabricated by using TSMC 0.18-μm 1P6M CMOS process with the core area 4.77 mm2. In WMAN, the proposed processor has demonstrated to perform four-stream 2048-point FFT within 52.6 μs at working frequency of 20MHz; moreover, the power dissipation is 40.97 mW, and the SQNR performance is above 48 dB. It is also showed that the power consumption is only 59.6 mW at working clock rate of 40MHz for WLAN by operating four-stream 128-point FFT, and is no more than 123.5 mW at clock rate of 104MHz for UWB by operating one-stream 128-point FFT.