Abstract
Low-density parity-check (LDPC) codes have great performance in water-fall region, but the error-floor phenomenon always excludes LDPC codes from many communication and storage systems. The phenomenon is resulted from some structures in LDPC codes' Tanner graph that disable the message-passing decoders to output correct codewords. For storage systems, high-rate LDPC codes and high-throughput are required. A technique is proposed to lower the error-floors of high-rate QC-LDPC codes with only a few extra number of iterations. In addition, the technique is also devised to cost only a few extra hardware resources. If a decoding failure happens, based on the unsatisfied check-nodes in the last iteration, it is known that there must be some error-bits in their adjacent variable-nodes. Combined with dominant trapping-set information, the amount of error-likely bits can be substantially reduced, even find the error-bits directly by look-up table (LUT). The proposed lowering technique aims at error-likely bits or error-bits to assign modified a posteriori probability (APP) to and send them back to a decoder to re-perform decoding process. This manner has a moderate quantity of computation and data storage, and could achieve a great error-floor performance. The (9216, 8352) and (18816, 16800)-irregular high-rate Quasi-Cyclic LDPC (QC-LDPC) code that have a coderate 0.906 and 0.892 have been used to demonstrate the proposed decoder can lower the error-floor by several orders in importance sampling simulations. And the result of hardware implementation in (9216, 8352)-layered decoding shows that the added gatecount of the error-floor lowering module is just a little.