Abstract
This thesis presents a high dynamic range linear-logarithmic CMOS image sensor pixel with threshold voltage cancellation scheme for reducing fix pattern noise (FPN) and tunable response curve for different environment. There are three innovations in this thesis. First, a novel five transistors pixel linear-logarithmic CMOS image sensor with adjustable linear region provides a tunable switching point between linear and logarithmic response without any post-processing to obtain the best image contrast in different environment. Second, A novel in-pixel threshold voltage cancellation scheme in three phases operation can eliminate the offset FPN from MOSFET’s threshold variation due to logarithmic mode operation at high illumination environment and improve the non-uniformity of the image efficiently. Third, a column shared-OPAMP with column amplifier is used in column circuit for solving the gain loss problem caused by source follower in convention active pixel sensor and providing a programmable gain to magnify pixel signal. The prototype high dynamic linear-logarithmic CMOS image sensor chip consisting of 100 x 100 5-T pixel array with n+/p-sub photodiode and pixel pitch as 6 x 6 μm2 with 32.54% fill factor and 3.3V operation has been designed and fabricated in TSMC 0.18μm CMOS 1P6M standard process. The measured results achieve a dynamic range of 143.89dB, a FPN related to sensitivity in logarithmic response (rms/log-sensitivity) of 1.96%, and a FPN related to full-swing in logarithmic response (rms/Vlog-swing) of 0.45%, respectively. Linear and logarithmic sensitivity are 651mV/lux-s and 55mV per decade of illuminance 50 frames/s. The temporal noise and power consumption are 0.7462mV and 1.88mW.