Abstract
In this thesis, we propose a high speed symmetric TDM switch system with VOQ. The STDM switch applies the architecture of the load balanced Birkhoff-von Neumann switch proposed in [10]. We fold this two-stage switch to reduce 50% hardware complexity, and then implement a 1.38 mm × 1.08 mm prototype switch fabric IC, including a full-customized 4×4 switch core, a digital switch pattern generator, and a set of CML I/O interfaces in 0.13μm CMOS technology. The digital pattern generator generates reconfigurable connection patterns for the 4×4 switch core to easily scale up to an N×N switch (N is power of 4). The full-custom design approximately improves 1.43 times of speed while saving 86% of the power and 80% of the area, compared with the traditional digital approach for switch IC with SERDES interfaces. Our simulation results show that a 4×4 switch fabric IC can achieve 40Gbps switching rate (10Gbps for each channel as the OC-192 standard) and consumes only about 134mW power. A terabit switch fabric can then be constructed by cascading the designed switch ICs with low power consumption. Furthermore, to provide a large capacity and high throughput VOQ for such a high speed STDM switch system, we introduce an ultra fast super capacity virtual VOQ architecture that supports data rate up to 9.6Gbps per channel with 2.048 Gb storage. This ultra fast super capacity virtual VOQ includes a first-in-first-out memory controller design with buffer manager functions to coordinates the packet flows of the switch fabric and four off-chip SDRAM chips efficiently and coherently.