Abstract
In this thesis, a high-speed and low-noise readout scheme for the 128Mb NOR-type Flash memories was designed. It has a higher readout speed than the NAND-type Flash memories. Based on cost considerations, the word lines (WL) in the memory array are maintained at a maximum length to minimize cell area, while the read speed is usually limited by the WL RC delay, i.e., the WL setup time. As a result of these constraints, the overall memory performance of a good sense amplifier as well as its sensing scheme can be greatly affected. In order to enhance the readout speed, all the noises that can possibly cause reading error must be eliminated or suppressed. It was found that the output buffers and the sense amplifier generate most of the noises. In this thesis, the read speed was improved by reducing the noise through a presetting scheme. Due to the large memory array of 128Mb chips, the parasitic resistance and capacitance were also considered critical to the read speed. With the new readout scheme, the TCE (chip enable time) and TAA (address access time) were improved from 85nsec to 80nsec during the simulation tests, with an added overhead in chip area of less than 0.02%. Moreover, the TPA (page access time) also improved by 4.76%, from 21nsec to 20nsec. The new readout circuit and operational scheme was verified using silicon through a 3P3M process and the results achieved the original design targets.