Abstract
This paper presents a high-throughput decoder architecture for non-binary low-density parity-check (LDPC) codes, where the q-ary sum-product algo- rithm (QSPA) in the log domain is considered. We reformulate the check-node processing such that an efficient trellis-based implementation can be used, where forward and backward recursions are involved. In order to increase the decoding throughput, bidirectional forward-backward recursion is used. In ad- dition, layered decoding is adopted to reduce the number of iterations based on a given performance. Finally, a message compression technique is used to reduce the storage requirements and hence the area. Using a 90-nm CMOS process, a 32-ary (837,726) LDPC decoder was implemented to demonstrate the proposed techniques and architecture. This decoder can achieve a through- put of 233.53 Mbps at a clock frequency of 250 MHz based on the post-layout results. Compared to the decoders presented in previous literature, the pro- posed decoder can achieve the highest throughput based on a similar/better error performance.