Abstract
Intra Prediction is the first process of H.264/AVC intra encoding, which compresses video by removing spatial redundancy. For high-resolution applications, we propose a highly parallel architecture of Intra Prediction Generation Engine (IPGE) to shorten the prediction time. An analysis derives that the required degree of Pixel-Level Parallelism (PLP) for luma 4x4 is 32 pixel/cycle, whereas for luma 16x16 and chroma 8x8 is 16 pixel/cycle. In addition, we propose a semi-reconfigurable architecture, a Processing Element Optimization Method (PEOM), and a Mode-Level Scheduling Scheme (MLSS) to reduce hardware usage. The proposed design has been implemented in Verilog RTL and synthesized targeted towards a TSMC 0.13μm CMOS cell library. Its gate count is 20.4K when running at 200MHz. In comparison with direct implementation, the proposed architecture reduces 90.2% of gate count. The engine for all luma 4x4 modes consumes 3.5K gates and takes 4 cycles to predict a 4x4 block; the engine for luma 16x16/chroma 8x8 modes consumes 11.7K gates and takes totally 96 cycles to generate a 16x16 macroblock. We have integrated the proposed design into an H.264/AVC intra encoder which can process 30fps 1080p HD video when running at 138MHz.