Abstract
In this thesis we investigate a defect modeling and testing methodology for intra-cell bridging defects from the layout perspective. For defect modeling, we incorporate a butterfly-based faulty schematic extraction and SPICE simulation to resolve the potential analog effect a bridging defect may cause. By doing so, a more realistic faulty circuit at the gate level can thus be generated for each defect under consideration. For defect coverage simulation and test vector generation, we further convert the defect detection requirements into a circuit form and then piggyback on traditional ATPG tools. Experimental results indicate that simple stuck-at test set can only achieve 86% defect coverage, while our method can further boost it to almost 100% for ISCAS85 benchmark circuits.