Abstract
Conventional NAND Flash memory with single-level cell architecture is implemented in hard-decision techniques such as Hamming or BCH codes to mitigate the effect of memory cell errors. However, it needs much more powerful error correction technique as these hard-decision techniques are not sufficient for multilevel technique and continuously scaled down cell size gradually. Low-density parity-check(LDPC) codes is a soft-decision technique with splendid error-rate performance. For NAND Flash applications, high-rate and low-cost decoders are required. Irregular (18624, 16704) and (18432, 16704) Quasi-Cyclic LDPC (QC-LDPC) code that has a code rate of 0.896 and 0.906 is used respectively. We presented a low-complexity LDPC Codec for NAND Flash implemented in two-stage encoder and a low-cost decoding architecture. In addition, encoder-decoder sharing is also implemented to reduce implementation complexity. Finally, we proposed a low-complexity check-node unit for decoder to optimize check-to-variable message to reduce storage complexity without error-rate performance loss. The LDPC Codec is implemented in TSMC 90-nm CMOS technology and the Two-Stage Encoder and the Decoder can achieve a throughput of 4.03Gb/s and throughput of 2.35Gb/s respectively at a clock frequency 166 MHz.