Abstract
In this thesis we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). Measurement results show the digitally controlled oscillator (DCO) is able to operate from 62 to 616 MHz. Combined with a programmable divider with its multiplicative factor from 1 to 2046, various frequencies could be synthesized for different applications. The Phase Detector (PD) is designed using a latch-based sense amplifier, leading to a nearly perfect one that is able to resolve a phase difference as minute as 1ps, while withstanding severe process variation. This ADPLL achieves low output clock jitter by a hybrid locking procedure. Firstly, the phase is locked quickly through a predictive phase-locking scheme. Then, the jitter is further minimized by a suppressive digital filter. Finally, a concept of frequency interpolation is utilized to enhance the resolution of the DCO so as to further reduce the phase error and jitter. Simulation results show that the jitter performance is very close to that of the free-running DCO and the phase error can be substantially reduced from 588ps to 21 ps where the reference clock is 1MHz and N is 128. Measurement results show that the jitterPk-Pk and jitterRMS are 56ps and 7.28ps, respectively, when the output clock of the ADPLL is running at 600Mhz.