Abstract
This Thesis presents a low-voltage operation and high energy efficient hybrid analog-to-digital converter (ADC) for instrumentation or biomedical systems applications. It is based on an energy-efficient hybrid ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine incremental ΔΣ conversion, to achieve target resolution performance. The proposed ADC operates at ultra-low supply voltage, 0.5V, to save power consumption. Novel switching technique in coarse SAR ADC is utilized to improve the power efficiency of the ADC in low voltage operation. In fine incremental ΔΣ modulator, switched-op amp (SO) technique is utilized to deal with low supply constraint of sub-1-V operation. The cascade of integrators feed-forward (CIFF) architecture reduces the signal swings of integrators, alleviating the requirement of high slew rate OTAs at low-power operation. Furthermore, SAR ADC comprises a 6 bit unary-weighted capacitor DAC array, which means every capacitor in the DAC array is equal to unit capacitor. Dynamic element matching (DEM) is used to average the mismatch and error on capacitor DAC array, hence achieve both low offset and high linearity. The proposed ADC is fabricated in TN90GUTM technology, achieving a 92.66-dB SNDR at 512-kHz sampling rate and 0.5-ms conversion time. The proposed ADC occupies core area of 0.301-mm2 and dissipates only 5.481-μW from a 500-mV power supply. The figure of merit (FoM) of overall ADC is 175.93-dB, which is competitive to state-of-the-art designs.