Abstract
This thesis presents a low-power SRAM design with Quiet-Bitline architecture by incorporating two major techniques. Firstly, we use a one-side driving scheme for the write operation to prevent the excessive full-swing charging on the bitlines. Secondly, we use a precharge-free pulling scheme for the read operation so as to keep all bitlines at low voltages at all times. HSPICE simulation on a 1K-bit SRAM macro shows that such architecture can lead to a significant 76% power reduction over a self-designed baseline low-power SRAM macro.