Abstract
Scaling down, power reduction and reducing threshold voltage of transistors are the future trends of process development. However, it also causes sub-threshold leakage current to become an increasingly large component of total power dissipation. Recently, multi-threshold voltage CMOS technology already has attracted more and more attention for its low power capacity. The technology can reduce efficiently the sub-threshold leakage current which low threshold voltage results in. Besides, it still can retain the original circuit performance without too large overhead. In this thesis, I apply MTCMOS technology to standard cell library design, besides, I inject stack transistors concept to enforce MTCMOS capacity of reducing sub-threshold leakage current. Standard cell library plays a really important role in digital circuit design; it is utilized universally for Cell-Based Design. A circuit designer can quickly use these elements of standard cell library to realize their design through Cell-Based Design flow. Therefore, the good or bad of cell library will directly affect the feature of designed circuits. Based on MTCMOS technology, I proposed two sets of standard cell libraries what they are used for TSMC 0.18μm and UMC 0.18μm process separately. By Cell-Based Design flow, I implemented two different test circuits with them. And through SPICE simulation, the results both proved that our standard cell libraries can lower efficiently power dissipation, especially for the improvement of sub-threshold leakage current.