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A Low Power and High Performance AHB-compliant EBCOT Architecture for JPEG2000 Encoding
Thesis

A Low Power and High Performance AHB-compliant EBCOT Architecture for JPEG2000 Encoding

Tien-Wei Hsieh
Masters, 國立清華大學, 資訊工程學系
2003

Abstract

JPEG2000影像壓縮標準 區塊編碼 內容產生器 算術編碼器 JPEG2000 EBCOT Context Formation Arithmetic Encoder
We propose a low power and high performance Tier-1 architecture of Embedded Block Coding with Optimized Truncation (EBCOT) in the JPEG2000 encoder. In the context formation, we use a parallel structure for low power consumption, a memory-saving algorithm to decrease memory access, a memory arrangement to utilize bandwidth efficiently, and a stripe-skipping method for performance benefit. In the arithmetic encoder, we adopt a modified probability estimation table and a forwarding method to implement pipelined architecture. We present a renormalization strategy that can save cycles during the coding process. Our design is easily integrated into the AMBA-based system as an accelerator. Compared with the best-known column-based method, we reduce the cycle count by 17%. Let the number of context-decision (CX, D) pairs be the lower bound on the cycle count, we have achieved 5% within the optimum.

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