Abstract
The research goal of this work is to develop a low-voltage, low-power, and high integration CMOS receiver for 5GHz wireless application. Meeting the goal of receiver integration in a CMOS technology requires innovation in architectures, circuits, and device modelings were introduced in this work. The IC was fabricated in a 0.18-μm CMOS technology. It combines low-noise amplifier, mixer, integer-N frequency synthesizer, automatic gain control, and low pass channel-select filter. A newly proposed operational amplifier that can boost 35dB in voltage gain without consuming extra power is used in the channel-select filter under low-voltage and low-power requirement. The cascade noise figure of the receiver is 7.67dB, and the cascade IIP3 is -14dBm. The phase noise of frequency synthesizer is 96.15dBc/Hz at 600kHz offset. In active mode, the receiver consumes 91mW on average from a 1.5V supply.