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A Margin Enhanced Current Sense Amplifier with Distance-Racing Scheme for Non-volatile Memories
Thesis

A Margin Enhanced Current Sense Amplifier with Distance-Racing Scheme for Non-volatile Memories

Li, Kai-Xiang
Masters, 國立清華大學, 電機工程學系所
2017

Abstract

裕度增強 感測放大器 非揮發性記憶體 Margin Enhanced Sense Amplifier Non-volatile Memory
Non-volatile memory (NVM) is very popular on storage memory market nowadays. Especially, Flash memory has already been the mainstream of NVM in recent years. The characteristics of Flash memory, such as high density, low cost, and low energy consumption, make it competitive on the market. However, Flash memory requires high voltage to program and erase, and the operation speed is still too slow to catch up with the requirements of next-generation inventions. Besides, there are some challenges which have to be overcome for the scaling of Flash memory, like coupling noise and large variation of threshold voltage. On the other hand, emerging non-volatile memories require lower operating voltage and have higher performance than Flash memory. Therefore, emerging NVMs have the ability to take over the next-generation NVMs. Some emerging NVMs (i.e. ReRAM or MRAM) are suitable for high performance and low supply voltage embedded applications, particularly for wearable devices with batteries. Nevertheless, the small R-ratio and high variation make some problems on sensing NVM devices in large capacity. So as to overcome the issues caused by small R-ratio and small LRS resistance, we propose a distance-racing read scheme to enhance the small margin by dual reference instead of conventional mid-point reference and suppress the input offset of sense amplifier under large BL current. The equivalent offset suppression of proposed scheme is 2.5~3x smaller than conventional works under large BL current. Moreover, the proposed scheme can achieve 1.2~1.6x faster speed than conventional works in long BL. In addition, the read yield can also be improved at least 30% in long BL. Finally, our proposed scheme is verified in a 1Mb ReRAM macro fabricated in TSMC 65nm CMOS process. The measured access time of ReRAM macro is 3.6ns at typical VDD = 1V and BL-length = 512.

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