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A Multiplier-based Cryptographic Processor Supporting AES and ECC
Thesis

A Multiplier-based Cryptographic Processor Supporting AES and ECC

Chieh-Lin Chuang
Masters, 國立清華大學, 電機工程學系
2006

Abstract

密碼學 先進加密標準 橢圓曲線加密 cryptography AES ECC
We propose an arithmetic unit supporting Advanced Encryption Standard (AES) and Elliptic Curve Cryptography (ECC). The arithmetic unit is based on a modified dual-field multiplier. The size of the multiplier is a design parameter for different throughput and area cost trade- offs. Our high-throughput implementation uses the 128x32 multiplier. The word-based Montgomery multiplication is modified for this asymmetric multiplier. The cryptographic processor supports the Electronic Code Block mode (ECB) and Cipher Block Chaining mode (CBC) for AES and Dual-field: GF(p) and GF(2n) for ECC. The operating frequency of the processor is 120 MHz by using TSMC 0.13um CMOS process. The throughput of AES are 1.56Gbps, 1.3Gbps, and 1.11Gbps for key size of 128, 192, 256 bits, respectively. A scalar point multiplication of ECC takes 2.27ms for 256-bit key in GF(p), and 1.11ms for 163-bit key in GF(2n),respectively.

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