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A Novel L2 Cache Indexing for Power Reduction in NoC Routers
Thesis

A Novel L2 Cache Indexing for Power Reduction in NoC Routers

Sung, Pin Hsuan
Masters, 國立清華大學, 資訊工程學系
2016

Abstract

晶片網路 快取記憶體索引 降低靜態功率 NoC cache indexing leakage power reduction
Network-on-chip (NoC) has been adopted as fast and efficient communication infrastructures in multi-core system for years. The on-chip routers play an important role in providing communication among cores. However, the routers consume considerable leakage power even if they are not in use. Applying power-gating to on-chip routers is a feasible approach to reduce the leakage power consumption. To take full advantage of router power-gating, we hope that the sleep period of routers can be as longer as possible. We propose a cache indexing algorithm such that accessing cache has the minimal impact on interrupting the sleep of idle routers. Experimental results show that our proposed method increases the sleep time of on-chip routers by 78.9% in average.

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