Abstract
In this thesis, we propose a P-P-N inverter based differential 10T SRAM cell capable of providing low power operation. Since cell stability is especially vulnerable to noise at sub-threshold voltage, the proposed cell avoids read disturb, improving cell stability significantly. Without cell stability concern, we strengthen the access transistors to ensure cell writability by employing reverse short channel effect. As transistor leakage becomes more prominent in nanometer technology, we introduce VGND biasing scheme to reduce the impact of data-dependent leakage current. Without complicate wordline control, the proposed cell allows multi-word on a wordline to increase cell density and to enable efficient error correction code (ECC). To verify the proposed cell, a 16Kb array of the proposed cell is fabricated in 90nm CMOS technology. For comparison, we also fabricate 2Kb array of previous work in our chip. Supply voltage for array and peripheral is separated to enable periphery voltage boosting and to measure the cell array leakage. Applying higher peripheral voltage not only enhances the chip operating speed but also resolve the operating limitation at low voltage while the cell array still operates at lower voltage, reducing leakage power significantly. Measurement results show the 16Kb array of the proposed cell can work successfully down to 285mV. By boosting periphery voltage to 0.4V, the proposed cell can work at a lower (265mV) voltage and operate at a higher frequency. The entire 16Kb array consumes 2.6uW leakage power at 300mV. After normalization, our cell consumes only 0.2X leakage current compared to previous work.