Abstract
With the feature size of semiconductor technology continues to reduce, how to keep a high level of reliability for memory products has become an important issue. Specifically, Error Detection and Correction (EDAC) techniques are commonly used in this scheme. It protects against soft errors and thereby enhances system reliability and data integrity. However, the conventional EDAC techniques would not be satisfied with memories with long codewords. Moreover, power reduction in memories like cells can be always done by keeping refreshing the frequency, but the data integrity should be considered with carefully. On account of the above issues, we propose an EDAC scheme for designing the parity check matrices which can be used on memories with different sizes of long codewords. The parity check matrix generator proposed in the paper can apply memories to reduce refreshing power consumption in single-error correcting, double error-detecting codes (SEC-DED). Power is minimized with little or no impact on area and delay, using degree freedom in selecting the parity check matrix of the error correcting code. It presents codes that use a smaller number of circuits and requires a shorter gate delay time than known codes. The overall construction methods are useful for systematic constructing the parity check matrices.