Abstract
In order to ensure that a circuit meets timing requirements, at-speed scan test is widely used to detect delay defects. However, at-speed scan test suffers from the test-induced yield loss. Because the switching activity of whole circuit during test mode is much higher than that during normal mode, the large portion of gates simultaneously switching contributes to serious IR-drop delay. Thus, propagation delay does not meet the timing constraint only at test mode. This IR-drop problem during test mode exacerbates delay defects and results in false failures. In this thesis, we take the X-‾lling approach to reducing the IR-drop e□ect during at-speed test. The main difference between our approach and the previous X-filling methods lies in two aspects. The first one is that we take the spatial information into consideration in our approach. The second one is how X-filling is performed. In previous work [7, 8, 9], a forward-propagation approach is taken, while a backward-propagation approach is proposed in this thesis. Compared with the previous work [9], the experimental result shows that we have 26% reduction in the worst IR-drop and 28% reduction in the average IR-drop. The IR-drop reduction also improves the IR-drop delay. We have 2.4% additional IR-drop delay in the critical paths as compared with the optimal path delay without considering IR-drop effect, while the previous work [9] has 3.4% additional IR-drop delay in the critical paths.