Abstract
In urgent demand of hardware architecture design for H.264 coder, pipeline scheme becomes one of most popular solutions. However, the unbalanced time consumption in pipeline stage reduced the throughput and hardware utilization. In this paper, we propose a pipelined architecture with macroblock-level parallelism within pipeline stages. To realize macroblock-level parallelism, higher level pipelining and proper job management between pipeline stages are designed. By efficient scheduling policy and system synchronization, data dependency of intra prediction and in-loop deblocking filter are prevented. In order to highly provide extensibility, possible modifications of low-level modules are employed to match up parallel architecture. To evaluate our proposed architecture, the design is prototyped by using FPGA module as target. From simulation result, while parallel architecture is employed and synthesized in 13MHz, up to 670 QCIF intra frames and 307 QCIF inter frames are decoded per second.