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A Platform-Based SOC Design Methodology and its Application on JPEG Decoding
Thesis

A Platform-Based SOC Design Methodology and its Application on JPEG Decoding

Kai-Yuan Jan
Masters, 國立清華大學, 資訊工程學系
2003

Abstract

系統單晶片 矽智財 影像壓縮 內嵌式 硬體加速器 高階合成 系統整合 軟硬體共同設計 SOC SIP AMBA Armenia Embedded High Level Synthesis SOPC AHB
We describe a platform-based design methodology for system-on-a-chip (SOC). A commercially available chip consisting of an embedded 32-bit RISC CPU core and a field programmable gate array (FPGA) module is used to implement applications that require both a program running on the CPU and hardware acceleration performed by the FPGA. The methodology consists of flow and tools for hardware/software partitioning, automatically synthesizing hardware accelerator, interface generation, software design/compilation, integrated hardware/software co-simulation, and whole system verification. We also present a case study of implementing an image decoder in a hardware/software co-design fashion on the platform using the described methodology. Computational intensive part of the application is methodologically identified and implemented as an AMBA compliant silicon intellectual property and successfully integrated with the software program running on the RISC CPU core. Experimental results show that the platform-based methodology is indeed effective for IP development/verification and fast prototyping.

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