Abstract
As the CMOS technology comes forward to nanometer scale, process variation increasingly deteriorates the yield of mass production. In [1], the authors proposed a row-based tunable design methodology which allows users to fine-tune the supply voltages of manufactured chips. The method presented in that thesis is able to mitigate the effect of process variation by fine-tuning the supply voltages for fabricated chips that originally fail the IC test. Yet, no effective algorithm has been proposed to determine how to adjust the supply voltages which would gain the sufficient chip speed and increase minimum power consumption. In this thesis we attempt to develop a voltage assignment algorithm for the decision of how to adjust the supply voltages for regulating failed chips. In the tunable circuits, the supply voltage (VDD), ground voltage (GND) and body bias can be adjusted up to +/- 0.2 Volt over the nominal voltage respectively, e.g. the voltage level of each cell could have three possibilities. If a chip has N tunable supply voltages, there are N3 solutions for this problem. Nevertheless, most of the solutions are not feasible or unable to regulate the failed chips. Hence, a voltage assignment algorithm is proposed to look for a solution that can satisfy the expected specification. We will follow the solution to adjust chip voltage. In the experiments, we have applied our method on the circuits under 180nm process node. We try to fix failed chips which are injected different amount of extra delay in a systematic way. In s38584, we can fix failed chips with up to 25.49% excessive delay over nominal timing spec. The range of dynamic power overhead is as low as -4.56%-43.07% compared to a typical voltage assignment case. Generally, chips with less excessive delay could result in less dynamic power overhead. Without this method, we can only conservatively apply the assignment best to timing, i.e. tune all VDD to 2V and GND to -0.2V for the 180nm process node, while this assignment would lead to more than 49% of the dynamic power overhead. The proposed algorithm can not only effectively fix failed chip in timing but reduce the power consumption.