Abstract
Process variation become increasingly serious as the semicondouctor technology keeps advancing toward nanometer scales. Recently, several post silicon tuning techniques have been widely used to compensate the variation of failing chips, though at the cost of increasing power consumption. In [1],the authors proposed a row-based tunable design methodology which allows users to fine-tune the supply voltages of manufactured chips. In this tunable circuits, the supply voltage (VDD) and ground voltage (GND) can be adjusted up to +/- 0.2 Volt over the nominal voltage respectively, e.g. the voltage level of each cell could have three possibilities. So we proposed a post-silicon voltage tuning methodology for process variation based on diagnosis results by this tunable circuit, which we can selectively tune up the voltages to increase the speed of parts of the circuits or tune them down to save power. First, once a chip was found failure by delay testing. Then we will use the diagnosis process [2] to get timing data of the chip. Finally, use voltage assignment program [3] to adjust VDD and GND by row to fix the timing violation which is affected by process variation. In the experiments, we have applied our method on circuit under 180nm process node and compare with the full chip tuning method. In s38584, the range of dynamic power overhead is -3.07% to 24.41% compared to a typical voltage assignment case by our method. And the range of dynamic power overhead is 0% to 49.43% compared to a typical voltage assignment case by full-chip tuning. We can saving as high as 25% of dynamic power by our method. And in b17, we can save as high as 25% of dynamic power by out method. The proposed algorithm can not only effectively fix failed chip in timing but reduce the power consumption.