Abstract
In recent years, higher and higher read/write speed is also required for high-performance portable equipment. Emerging NVMs have the potential to overcome the write performance and scalability limits of currently dominant Flash memories. The write time of RRAM can be less than 10ns, the read time will be bottleneck for high-speed applications. Besides, the read BL bias of RRAM cells has to be lower than 0.3V to prevent disturb, however, BL voltage of conventional current sensing circuit is sensitive to process and temperature variations. In addition, the reference cell resistance variation will cause read failure due to reference current variation. In this work, we propose a process variation tolerant read circuits featuring detection and compensation of process and temperature variations to avoid read disturbance, narrow-distribution reference generation scheme reduces the probability of read failure, and BL charging speed enhancement scheme shortens BL charging time. The proposed schemes enable high-speed and reliable read operation. An asynchronous 4M-bit RRAM testchip were fabricated in 0.18μm, 5-metal CMOS technology and ITRI resistive device technology with a nominal supply voltage of 1.8V for read circuits. We measured the current distribution of 2048 cells and 512 reference generators, the reduction of reference current variation is about 45% compared to normal LRS cell current distribution. The measured read time of random access and burst access are 7.2ns and 3.6ns respectively.