Abstract
We propose a variable block-size motion estimator (VBSME) down to quarter-pixel precision for the next generation video coding standard H.264. The proposed motion estimator consists of a full-pixel precision part and a sub-pixel precision part. The former is a 2D systolic array with 256 processing elements (PE) employing a computation result reuse methodology. Its full search algorithm can complete matching a candidate macroblock every clock cycle. It figures out the sum of absolute differences (SAD) and motion vectors (MV) at full-pixel precision for the sub-pixel precision part. The sub-pixel precision part is a mathematical model to refine the SADs and the MVs to quarter-pixel precision. Synthesized into a TSMC 0.13μm CMOS technology, it takes 195K gates at 50MHz to process 720x480 video sequences at 30 frames per second (fps).