Abstract
The technology scaling down has provided much more gate count in silicon chips. The contraction of minimum channel length and decrease of power supply voltage have benefited digital circuits to smaller area, higher operation rate and lower power consumption. However, this progress of technology presents a number of challenges in mixed signal IC design. In this thesis, a new 1V rail-to-rail comparator with low noise and low power consumption is presented. We utilize current mirrors to overcome the common issue, kickback noise. A new adaptive power control (APC) technique is also proposed to minimize the power dissipation of the comparator. Moreover, it provides an optimized and stable power dissipation irrelative to process and bias variation. A 1V rail-to-rail SAR ADC prototype, targets for biomedical applications, has been implemented in 0.18μm TSMC CMOS technology. It consumes 2.86 μW at 250kS/s and the figure of merit is 85.7 fJ/conversion-step. It shows that this work efficiently reduces 52% to 80% power consumption of the dynamic latched comparator at 500kS/s to 125kS/s.