Abstract
It is well-known in the industry that the outcomes of Electronic Design Automation(EDA) tools can be further fine-tuned by carefully trimming gate-level cell library at logic synthesis stage. With better selections of library cells, the Synopsys Design Compiler can achieve better area reduction while maintaining given design constraints. Conventionally, this fine-tuning procedure is performed manually and empirically for each design since the library needed for each design can be different. The process could be time consuming and inefficient. In this work, we propose a reinforcement learning based logic synthesis framework to achieve further area reduction while maintaining given design constraints. In our framework, we used a policy-based technique to explore a better library selection. First, a target library as well as the given design is synthesized by Synopsys Design Compiler. After that, the timing and area information obtained from the synthesized netlist is send to the machine learning model. Then the model will modify the target library based on the obtained information. The framework will be executed iteratively and the machine learning model will learn the best library for the given design after convergence. Experimental results show that we can obtain up to 33.07% area reduction on ITC’99 RTL circuits with TSMC 40nm technology gate-level cell library.