Abstract
In the IC industry, chip design cycles are becoming more compressed, while designs themselves are growing in complexity. Functional specifications are often modified late in the design cycle, after placement and routing are complete. These trends necessitate efficient methods to handle late-stage engineering change orders (ECOs) to the functional specification, often in response to errors discovered after much of the implementation is finished. In this thesis, we propose a three-stage algorithm for generating a minimal logic difference between an original circuit and a modified circuit. Our method has three different stages and we perform them in order to produce a better patch. In the first phase, we search from the primary outputs to find structural equivalence between the original circuit and the modified circuit. In the second phase, we modify DeltaSyn[1] to use a SAT solver to identify logic equivalence near the input-side boundary of the changes. In the third phase, we create levels in each gate. According to levels, we check logically equivalent and choose replaced gates. After the three different stages, a gate-recycle[2] process performs the patch minimization in the final step. Encouraging experimental results are obtained by our method.