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A Scalable Approach to Correctness Analysis and Optimization for Probabilistic Boolean Circuits
Thesis

A Scalable Approach to Correctness Analysis and Optimization for Probabilistic Boolean Circuits

Yu, Zheng-Shan
Masters, 國立清華大學, 資訊工程學系
2012

Abstract

機率邏輯 Probabilistic CMOS Probabilistic Boolean Circuit Correctness
Traditionally, we expect that the designs can be performed without errors. However, for error-resilience applications, e.g., image processing, 100% correctness is not a must. An interesting study reveals that if we do not pursue 100% correctness for the operations, the energy consumption would be significantly reduced. Recently, Probabilistic Boolean Circuits (PBCs) have been proposed. However, prior to developing the algorithms for PBC optimization, having an efficient method for correctness analysis is necessary. In this paper, we propose a statistical approach that efficiently and accurately evaluates the correctness of PBCs. The experimental results show that the proposed approach performs about 122 times faster than the golden result method on average with little correctness difference. We also propose an optimization strategy that assigns probabilistic gates with little correctness suffering, e.g., when the percentage of probabilistic gates in C1355 is <60%. Thus, the proposed approaches are very promising.

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