Abstract
In this thesis, specification study, system simulation, architecture design and circuit design along with chip implementation of a low complexity and low power MIMO detector for wireless communications with scalability is presented. Several types of MIMO systems for wireless communication are discussed and the related receiving techniques such as linear and non-linear detection methods are also introduced. Based on these well-studied detection methods, a scalable MIMO detector architecture with low complexity and high performance is proposed. The proposed architecture is low complexity by dividing a large MIMO detector into two parts called core part and residual part, and then the general detection method such as Ordered Successive Interference Cancelation (OSIC) can be applied in each part with smaller dimension. To enhance the detection performance, a Simplified Maximum Likelihood (SML) is also proposed in the core part. Moreover, the proposed architecture is easily scalable because the detector is divided into several basic building blocks. Simulations are based on the MIMO fading channel model with white noise. The elements in the channel matrix are assumed i.i.d. complex Gaussian random variable with zero mean and variance of 0.5 per dimension. Simulations are under flat fading and quasi-stationary environment. To minimum the area and power of the proposed MIMO detector, some hardware simplifications are applied after cost analysis. The proposed detector is implemented with the synthesizable RTL by cell-based ASIC design flow. The detector chip is fabricated with a TSMC 0.13 um 1P8M technology. The maximum operational clock rate is simulated at 62.5 MHz. Power consumption is 50 mW at 1.2 V supply voltage under the maximum clock rate. The chip can support two up to four transmitted streams and two up to six received streams with BPSK, QPSK, 16-QAM and 64-QAM modulation types. After fabrication the IC, several enhancements are also proposed such as advanced low power technique and throughput enhancement. These provide a chance to implement an excellent MIMO detector chip in the future.