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A Separate Code Cache Model for a Parallel Multi-Core System Emulator Based on QEMU
Thesis

A Separate Code Cache Model for a Parallel Multi-Core System Emulator Based on QEMU

Chien, Chia-Hung
Masters, 國立清華大學, 資訊工程學系
2010

Abstract

二進制程式碼快取 平行 系統模擬器 多核心 QEMU Code Cache parallel system emulator Multi-core QEMU
QEMU is a fast processor emulator by adopting dynamic binary translation techniques to achieve high emulation efficiency. With QEMU, various operating systems and programs created for one ISA can be run on a machine with a different ISA. However, the current design of QEMU is only suitable for single-core processor emulation. When executing a multi-threaded application on a multi-core machine, QEMU emulates the execution of the application in serial and cannot take advantage of the parallelism available in the application and the underlying hardware. In this work, we propose a novel design of a multi-threaded QEMU, called P-QEMU, which can effectively deploy multiple simulated virtual CPUs on the underlying multi-core machine. The main idea of the design is to add a Separate Code Cache model to the execution flow of QEMU. To evaluate the design, we emulate an ARM11 MPCore by running P-QEMU on a quad-core x86 i7 system and use SPLASH-2, PARSEC, and CoreMark as benchmarks. The experimental results show that the performance of P-QEMU is, on average, 3.79 times faster than that of QEMU and is scalable on the quad-core i7 system for the SPLASH-2 benchmark suite.

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