Abstract
In recent years, the growth of IoE devices requires non-volatile memory (NVM) for its large capacity, high speed, low energy and low cost. Flash memory has already been the mainstream of NVM since last century. However, flash memory doesn’t operate fast enough and cannot be accessed randomly. Furthermore, as technology proceeding, flash memory faces difficulties of scaling down to nanometer scale. Necessarily, researchers starts to seek candidates for replacing flash memory. Among all of the inventions, 1T1R ReRAM seems to be a promising choice due to its low write energy, fast speed and logic-process compatibility. 1T1R ReRAM cell is suitable for high speed and low supply voltage embedded applications, particularly for IoE devices with batteries. As size of ReRAM shrinking, cell resistance (RCELL) of ReRAM becomes higher and the wide write time distribution and RCELL reduces the R-Ratio (RH/RL) between high-RCELL state (HRS, RHRS) and low-RCELL state (LRS, RLRS). Thus, ReRAM memory macro suffers the following problem during read : 1.Small read sensing margin (ISM) due to small R-Ratio and process variation 2.Long access time (TCD) due to small R-Ratio Here, we propose Dynamic Trip-Point-Mismatch Sampling Current Sense Amplifier (DTPMS-CSA) to solve the reading problem. DTPMS-CSA achieves 4.8x~7.1x smaller IOS than conventional Current-Latch CSA (CL-CSA). In addition, DTPMS-CSA achieves at least 1.6x faster speed and 3.1x better yield than the conventional one. We implement our proposed SA at a 2Mb 65nm ReRAM macro. At typical VDD and BL-Length=512, DTPMS-CSA achieved 2.6ns read access time. Even more, DTPMS is 1.19ns faster than that of conventional CL-CSA.