Abstract
Abstract Due to the growing demand of consumer electronics in recent years, demand of non-volatile memories continues to grow up. The most common large capacity memory is Flash. However, as the technology process advances, Flash memory has many challenges in process scaling. Therefore, next generation emerging non-volatile memory has become the replacement solution for Flash memory. In many researches, non-volatile resistive random access memory (RRAM) is a prominent solution device. It stores data by its high resistance state and low resistance state. Its advantages include CMOS-logic compatibility, small area size and low write power consumption. In the latest array structure, 3D stacking can further increase the density of RRAM. Nonetheless, either the resistance variation of RRAM or the sneak current of 3D RRAM structure can decrease the reading yield. The sneak current issue gets worse when array size continues to be large and it is also data-dependent. Our proposed sensing scheme mainly detects the background sneak current and eliminates the voltage offset due to sneak current. We also choose a special reference voltage to enlarge sensing margin . We implemented the sensing scheme in 65nm 12kb test chip. In normal VDD operation, correct data can be read out even sneak current is over 19uA. The voltage offset due to sneak current cancellation function can be verified in this chip.