Abstract
Register transfer level (RTL) is commonly used for a integrated circuit (IC) design. We can obtain the hardware structure and dataflow more clearly and efficiently from RTL. The high-level information can be used for a path selection at the gate level, so we can select paths more efficiently. In this thesis, we propose a method to extract constraints form register transfer level circuits. The constraints include control signals, port names, register names and data-path signals which determine the operation of circuits. We select control flow paths from the control flow graph (CFG) of each RTL circuit and get the control signals for each control flow path. Then, we get the dataflow according to each control flow path. According to the constraints extracted from RTL, we use them for a path selection tool at the gate level. The paths selected by the path selection tool according to the constraints are functionally needed to be tested. The experimental results show that the characteristics of circuits, so we can observe the differences of paths according to their circuits and constraints. The percentage of the paths functionally needed to be tested is 70% ˜ 90% in the circuits.