Abstract
Static Random Access Memory (SRAM) cell stability is a key challenge in sub-threshold SRAM design, in which read disturb and half-select disturb have been major issues. In this thesis, we propose a 9T cell with 3key features, Static Noise Margin (SNM) free, dual-port access and bit-interleaving structure to eliminate half-select disturb. With additional read port, it can isolate the storage node from bit-line during read access, thereby improving the SNM. The proposed cell also provides efficient bit-interleaving structure to avoid half-select disturb issue. In addition, the 9T SRAM cell can perform read and write operations simultaneously, hence dual-port SRAM function can be implemented with better efficiency. To be able to control the word-line efficiently, where the word-line pulse width varies at different process, voltage and temperature (PVT) conditions, we developed a dummy cell to detect the access completion both in read and write modes. Thus, the asynchronous operations can be achieved easily. Using TSMC 65nm low-power spice models, the purposed cell is shown to reduce the access delay and achieve much smaller static power as compared to other approaches.