Abstract
With the advent of deep submicron technology and system-on-chip (SOC) design methodology, complex systems can be integrated into a single chip. SOC designs which usually consist of reusable cores from multiple resources are becoming a trend of IC industry. However, complex designs also pose more testing problems than the conventional VLSI designs. To prevent the testing from becoming the bottleneck of SOC manufacturing process, not only the cores but also the core tests should be reusable. Therefore, the IEEE P1500 standard is being proposed to make SOC and test reuse in a `play-and-plug' way. We propose a test control architecture for SOC designs with IEEE P1500 test wrapper in this thesis. This architecture can support both serial interface layer and parallel test access mechanisms. The major advantages of the test control mechanism have low area overhead and protocol use to handle the test process is simple. A compiler for the test controller is implemented. It generates the synthesizable RTL code, synthesis script of the RTL code and the test bench used to verify the test control architecture. This design has been applied to an industrial practice. The test chip is composed of four embedded logic cores, six embedded SRAM cores and some user-defined logics. Experimental results show that the area overhead of the test controller, the parallel test access mechanism and the test wrapper is low, which about $6.14\%$ in total.