Abstract
Handheld electronics, car electronics, and portable biomedical electronics require nonvolatile memory for code storage. In order to achieve high performance operation, fast program code access for microcontroller unit (MCU) is prerequisite. By integrating embedded memory with MCU, higher processing performance can be achieved. Flash memory is the mainstream embedded nonvolatile memory. However, Flash memory cannot achieve high speed write operation due to sequential write。It also requires high voltage (>10V) to perform write operation。Furthermore, it is difficult to scale down Flash in deep nanometer scale. Thus, the research and development of emerging nonvolatile memory is necessary and becoming popular topic. Among those emerging memories, Resistive Random Access Memory (RRAM) is one of the most promising candidates. It has attractive characteristics such as low write voltage, fast write speed, low write energy, and good retention time. However, two major challenge should be solved for RRAM: 1. Reducing the area of cell select switches, while satisfying write current requirements. 2. Maximizing ICELL for yield and speed, while maintaining a small voltage drop across the RRAM device (VR) to prevent read disturbance. In this work, a logic process compatible vertical parasitic BJT (VPBJT) is used to reduce the macro area. Comparing to CMOS array, the VPBJT can achieve 4.5X smaller macro area. However, BJT is sensitive to temperature variation which affects read reliability. We propose a thermal-aware bitline (BL) voltage bias scheme (TABB) for current-mode read with 4.7x larger cell current, and a 1.6x faster read speed. We fabricated 0.18μm 1Mb and 65nm 2Mb VPBJT RRAM macros to confirm the efficacy of the proposed sensing scheme. 4.2ns and 4.7ns access time have been measured for 0.18μm and 65nm macro respectively, which is the fastest random read speed among reported Mb-scaled NVM macros.