Abstract
Previously, logic synthesis and physical design have been performed separately. During logic synthesis, only gate delays are available when estimating interconnection delays. The synthesis result is only as good as the estimation accuracy. As the IC industry moves towards deep sub-micron era, interconnection delay will overwhelm gate delays. Accurately estimating without a link to the layout synthesis is impossible since the interconnection delays heavily depend on the layout. Therefore, a feasible solution would be to integrate logic and physical design. In this thesis, we address several timing-driven approaches and present an integrated chip implementation flow that incorporates a floorplanning-guided soft-macro placement and re-synthesis method for area and timing improvement. In the timing closure design flow, the major deep sub-micron layout electrical characteristics are also considered. First, we present a performance-driven soft-macro clustering and placement method that utilizes the Hardware Description Language(HDL) design hierarchy. Second, a timing closure flow is developed to exploit the interaction between logic synthesis and physical design. During each iteration, soft-macros are re-synthesized with either a relaxing or a tightening timing constraint based on the post-layout timing information from the previous iteration. Doing so allows us to produce area-efficient designs while satisfying the timing constraints. Experiments on several industrial designs ranging from 75K to 230K gates demonstrate that the proposed method reduces critical-path delay by an average of 22\%.