Abstract
Embeddedmemory is one of themost widely used cores in current system-on-chip (SOC). Memory cores are more and more compact, and dominate the silicon area and yield of the chip. However, caused by process variation and some defects, how to maintain the yield of memory is an important issue. Today, redundancy repair methodology is widely used to enhance memory yield. Different memory and redundancy architecture may lead to different efficiency of redundancy repair and thus final yield under a specific process. In this work, we propose a redundancy analysis (RA) algorithm simulation tool to evaluate the efficiency of repair. The RA simulator reports the repair rate (the ratio of the reparable memory count to the defective memory count) and yield (after repair) with given RA algorithm, associated memory configuration, and redundancy structure. We have defined a systematic representation method to describe memory architecture and redundancy constraint. With our tool, the user can easily evaluate and plan the memory architecture and redundant elements. To reduce the simulation time, some early terminate criteria are developed and implemented. Experimental results show that our RA simulator can effectively evaluate the RA algorithm and memory structure, considering redundancy constraints.