Abstract
Serial link interconnect catches lots of attention for on-chip bus design due to its advantages over multi-bit parallel interconnect in terms of crosstalk, skew, and area cost. However, serializing multi-bit parallel bus tends to increase bit transition and power dissipation. In this paper, we propose a bit-revert transition inversion (BTI) coding scheme that can reduce up to 12% transitions compared to the traditional serial-encode (SE) scheme. The BTI coding scheme is simple and exactly the same for the encoder and decoder. The resulting architecture needs less gate count compared to previous transition inversion coding scheme. However, an extra indication bit is added in every codeword to represent inversion occurrence. This extra bit increases the transmission overhead and the bit transitions. We further propose an embedded transition inversion (ETI) coding scheme that uses the phase difference between clock and data in the transmitted serial data to resolve the issue of the extra indication bit. This ETI coding scheme can reduce up to 31% of transition compared with the ES scheme. From our analysis and simulation results, our proposed coding scheme produces low bit transition on the serial link for different kinds of data pattern on the parallel bus. Multiplexing more bit per serial link increases the transition reduction that becomes constant. In addition, increasing the line spacing reduces the coupling capacitance between adjacent lines. Thus, an optimum degree of multiplexing and an optimum width and spacing exist, which minimizes the bus energy dissipation and maximizes the bus throughput per unit area. Using the optimum degree of multiplexing, optimum width and space for maximum throughput per unit area and ETI coding scheme, our proposed scheme reduces 75% energy compared to the parallel bus line.