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A Two-Result-Per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder
Thesis

A Two-Result-Per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder

Yuan-Chun Lin
Masters, 國立清華大學, 資訊工程學系
2006

Abstract

視訊壓縮 去區塊 濾波器 高畫質 Video deblocking filter H.264 QFHD
We propose a high-performance hardwired Deblocking Filter (DF) for H.264/AVC video decoding. To fulfill the demand of ultra high throughput for QFHD (4x Full 1080HD), we optimize processing cycle, external memory access and working frequency of our architecture. Our Two-Result-Per-Cycle edge filter achieves near optimal processing cycle. It takes only 48 clock cycles to filter a macroblock in best case and 100 in worst case. Furthermore, it can save most unnecessary off-chip memory traffic with efficient on-chip memory. Our circuit supports skip mode to further reduce processing cycles and off-chip memory access in inter-predicted frame. Also it employs a 5-stage pipelined, and hardware-shared dual-edge-filter to generate two filtering results every cycle. Running at 195 MHz, it can support QFHD @ 60fps application.

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