Abstract
Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A TSV could suffer from two major types of parametric faults – a resistive open fault, or a leakage fault. Unlikely to stuck-at faults, these parametric faults do not destroy the functionality of a TSV completely but degrade its quality or performance. Based on our previous test structure, called VOT (Variable Output Threshold) scheme for delay faults, we propose a unified in-situ characterization flow for both parametric fault types of a post-bond TSV. With this flow, one can easily derive a more insightful assessment of a parametric fault in production test, process monitoring, and diagnosis-driven yield learning. A scalable test infrastructure indicates that the test time is modest at only 17.2 ms for 1024 TSVs and 648.8 ms for 32,768 TSVs when the test clock is running at 10MHz.