Abstract
With technology evolutions, the complexity and size of VLSI circuits keep increasing. The delay problem becomes more serious than before. How to efficient and complete detect the delay defects is a big challenge. In this thesis, we propose a Universal testing methodology to test FPGA delay defects. Because the number of path delay fault is too large that we can’t cope with it, we propose a novel delay fault model to model the delay defects. We name it as single-line-segment delay fault model. If the delay defect is large enough to cause some paths exceed the specified duration, the fault occur. Our initial test configurations are to cover all of these faults. The configuration time is still dominative the test time. We propose some reduce method to reduce the initial test configurations but they still cover all faults. In our method, the configuration is dominated by the width of single-length-line, the number of FFs and LUTs, and the number of CLB input and output. For Xilinx XC4000 FPGA, we take 24 configurations to cover all faults. When the fault size is large than five, we achieve 100% fault coverage.