Abstract
As the CMOS technology coming to nanometer scale, process variation play an important role in yield of production. It and defects can reduce a product’s parametric yield. Yet, even we have categorized chips with above influences, there is a lack of methods to further analyze these effects. In this paper, we propose to build a regression model from failed chips under the influence of systematic variations. The inputs of the model are the delay measurements of failed paths. And the proposed model will use circuit features to generate delay deviations, which can in turn be injected back to circuits for timing analysis considering variations. Thus, we can predict the probability of other possibly failing paths in order to select candidates for further test generation. Therefore, test quality is improved for next batch of chips or better confidence level is achieved for next design cycle.